1. Field of the Invention
The present invention relates to a semiconductor wafer processing method for manufacturing a stacked device chip composed of a plurality of stacked semiconductor devices.
2. Description of the Related Art
In a semiconductor device fabrication process, a plurality of crossing division lines called streets are formed on the front side of a semiconductor wafer to thereby partition a plurality of regions where devices such as ICs and LSIs are respectively formed. The semiconductor wafer is divided into chips along the division lines, thereby manufacturing a plurality of individual semiconductor devices. The semiconductor devices thus manufactured are widely used in various electrical equipment.
With a reduction in size and thickness of electrical equipment in recent years, it is required to also reduce the size and thickness of a semiconductor device package, and high-density mounting is therefore required. As a technique for integrating a plurality of semiconductor devices in one package, there is a three-dimensional mounting technique such that a plurality of semiconductor device chips are stacked in a vertical direction. In a conventional three-dimensional mounting technique, the semiconductor device chips are connected to each other by wire bonding or the semiconductor device chips and an interposer are connected to each other by wire bonding. The connection by wire bonding has a problem such that an inductance is increased by the length of wires and this technique is therefore unsuitable for high-speed transmission of signals. Another problem on wire bonding is such that the semiconductor device chips must be stacked without the contact of the wires, causing the difficulty in reducing the size of the package.
As a new three-dimensional mounting technique, there has recently been developed a stacking technique such that a plurality of semiconductor device chips are stacked on a semiconductor device wafer (Chip On Wafer) and a through electrode extending between a semiconductor device of each semiconductor device chip and each semiconductor device of the semiconductor device wafer is formed to connect these semiconductor devices to each other. To reduce the thickness of such a stacked chip package, it is desirable to reduce the thickness of each semiconductor device chip to be stacked on the semiconductor device wafer to 50 μm or less, for example. For the purposes of facilitating the handling of the semiconductor device wafer and reducing the risk of damage to the semiconductor device wafer, the semiconductor device wafer is attached to a substrate before reducing the thickness of the semiconductor device wafer and performing various processings.
In forming the through electrode, it is necessary to perform heat treatment such as an insulating film forming step including heating at about 450° C. and a reflow step including heating at about 200° C. Conventionally, after the semiconductor device wafer is attached to the substrate such as a glass substrate by using a heat-resistant adhesive, the semiconductor device wafer is subjected to a metal film forming step and heat treatment.